HD6417034 Datasheet, PDF (210/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

(c) Refresh cycle + bus cycle
The bus is never released during a refresh cycle and the following bus cycle ((a) or (b)
above)) (figure 8.46).
Refresh cycle 1 bus cycle
Cycle during which bus
is not released
Figure 8.46 Refresh Cycle and Following Bus Cycle
2. Bus release procedure
The bus release procedure is shown in figure 8.47. Figure 8.47 shows the case where BREQ is
input one state before the break between bus cycles so that tBRQS is satisfied. In the SH7032
and SH7034, the bus is released after the bus cycle in which BREQ is input (if BREQ is input
between bus cycles, after the bus cycle starting next).
CK
BREQ
t_BRQS
BACK
RD, WR
RAS, CAS
CSn
A21 to A0
Bus cycle
t_BRQS
t_BACD1
t_BACD2
t_BZD
t_BZD
Bus release
Bus cycle
Strobe pin:
high-level output
Address & data
strobe pins:
high impedance
The bus is released after the bus
cycle in which BREQ is input
(if BREQ is input between bus cycles,
after the bus cycle starting next).
Figure 8.47 Bus Release Procedure
Bus cycle restart
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