HD6417034 Datasheet, PDF (271/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

• Bit 3 (PWM Mode 3 (PWM3)): PWM3 selects the PWM mode for channel 3. When the
PWM3 bit is set to 1 and PWM mode is entered, the TIOCA3 pin becomes a PWM output pin.
1 is output on a compare match of general register A3 (GRA3); 0 is output on a compare match
of general register B3 (GRB3). When complementary PWM mode or reset-synchronized PWM
mode is set by the CMD1 and CMD0 bits in the timer function control register (TFCR), the
setting of this bit is ignored in favor of the settings of CMD1 and CMD0.
Bit 3: PWM3
0
1
Description
Channel 3 operates normally
Channel 3 operates in PWM mode
(Initial value)
• Bit 2 (PWM Mode 2 (PWM2)): PWM2 selects the PWM mode for channel 2. When the
PWM2 bit is set to 1 and PWM mode is entered, the TIOCA2 pin becomes a PWM output pin.
1 is output on a compare match of general register A2 (GRA2); 0 is output on a compare match
of general register B2 (GRB2).
Bit 2: PWM2
0
1
Description
Channel 2 operates normally
Channel 2 operates in PWM mode
(Initial value)
• Bit 1 (PWM Mode 1 (PWM1)): PWM1 selects the PWM mode for channel 1. When the
PWM1 bit is set to 1 and PWM mode is entered, the TIOCA1 pin becomes a PWM output pin.
1 is output on a compare match of general register A1 (GRA1); 0 is output on a compare match
of general register B1 (GRB1).
Bit 1: PWM1
0
1
Description
Channel 1 operates normally
Channel 1 operates in PWM mode
(Initial value)
• Bit 0 (PWM Mode 0 (PWM0)): PWM0 selects the PWM mode for channel 0. When the
PWM0 bit is set to 1 and PWM mode is entered, the TIOCA0 pin becomes a PWM output pin.
1 is output on a compare match of general register A0 (GRA0); 0 is output on a compare match
of general register B0 (GRB0).
Bit 0: PWM0
0
1
Description
Channel 0 operates normally
Channel 0 operates in PWM mode
(Initial value)
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