HD6417034 Datasheet, PDF (224/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

9.3 Operation
When there is a DMA transfer request, the DMAC starts the transfer according to the
predetermined channel priority order; when the transfer end conditions are satisfied, it ends the
transfer. Transfers can be requested in three modes: auto-request, external request, and on-chip
module request. Transfer can be in either single address mode or dual address mode. The bus
mode can be either burst or cycle steal.
9.3.1 DMA Transfer Flow
After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA
transfer count registers (TCR), DMA channel control registers (CHCR), and DMA operation
register (DMAOR) are set, the DMAC transfers data according to the following procedure:
1. Checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0).
2. When a transfer request arrives and transfer is enabled, the DMAC transfers one transfer unit
of data. (For an auto-request, the transfer begins automatically when the DE bit and DME bit
are set to 1. The TCR value will be decremented by 1.) The actual transfer flows vary by
address mode and bus mode.
3. When the specified number of transfer have been completed (when TCR reaches 0), the
transfer ends normally. If the IE bit in CHCR is set to 1 at this time, a DEI interrupt is sent to
the CPU.
4. When an address error occurs in the DMAC or an NMI interrupt is generated, the transfer is
aborted. Transfers are also aborted when the DE bit in CHCR or the DME bit in DMAOR
changes to 0.
Figure 9.2 shows a flowchart of this procedure.
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