HD6417034 Datasheet, PDF (376/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

• Bit 7 (Watchdog Timer Overflow (WOVF)): WOVF indicates that TCNT has overflowed
(from H'FF to H'00) in watchdog timer mode. It is not set in interval timer mode.
Bit 7: WOVF
0
1
Description
No TCNT overflow in watchdog timer mode
(Initial value)
Cleared when software reads WOVF, then writes 0 in WOVF
Set by TCNT overflow in watchdog timer mode
• Bit 6 (Reset Enable (RSTE)): RSTE selects whether to reset the chip internally if the TCNT
overflows in watchdog timer mode.
Bit 6: RSTE
0
1
Description
Not reset when TCNT overflows
(Initial value)
LSI not reset internally, but TCNT and TCSR reset within WDT.
Reset when TCNT overflows
• Bit 5 (Reset Select (RSTS)): RSTS selects the type of internal reset generated if TCNT
overflows in watchdog timer mode.
Bit 5: RSTS
0
1
Description
Power-on reset
Manual reset
(Initial value)
• Bits 4–0 (Reserved): These bits are always read as 1. The write value should always be 1.
12.2.4 Notes on Register Access
The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in that they
are more difficult to write. The procedures for writing and reading these registers are given below.
Writing to TCNT and TCSR: These registers must be written by a word transfer instruction.
They cannot be written by byte transfer instructions. TCNT and TCSR both have the same write
address. The write data must be contained in the lower byte of the written word. The upper byte
must be H'5A (for TCNT) or H'A5 (for TCSR) (figure 12.2). This transfers the write data from the
lower byte to TCNT or TCSR.
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