HD6417034 Datasheet, PDF (54/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

2.1.2 Control Registers
Control registers consist of the 32-bit status register (SR), global base register (GBR), and vector
base register (VBR). The status register indicates processing states. The global base register
functions as a base address for the indirect GBR addressing mode to transfer data to the registers
of on-chip supporting modules. The vector base register functions as the base address of the
exception vector area including interrupts.
31
SR
31
31
9 8 7 6 5 4 321 0
M Q I3 I2 I1 I0 S T SR: Status register
GBR
T bit: The MOVT, CMP, TAS, TST,
BT, BF, SETT, and CLRT instructions
use the T bit to indicate true (1) or
false (0). The ADDV, ADDC, SUBV,
SUBC, DIV0U, DIV0S, DIV1, NEGC,
SHAR, SHAL, SHLR, SHLL, ROTR,
ROTL, ROTCR and ROTCL
instructions also use the T bit to indicate
carry/borrow or overflow/underflow
S bit: Used by the MAC instruction.
Reserved bits. These bits always read 0.
The write value should always be 0.
Bits I3–I0: Interrupt mask bits.
M and Q bits: Used by the DIV0U, DIV0S,
and DIV1 instructions.
Global base register (GBR):
0 _{Indicates the base address in indirect}
GBR addressing mode. The indirect GBR
addressing mode is used to transfer data
to the on-chip supporting module register
area, etc.
VBR
0 Vector base register (VBR):
Stores the base address of the exception
vector area.
Figure 2.2 Control Registers
18