HD6417034 Datasheet, PDF (234/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

External address bus
SuperH microcomputer
DMAC
External data bus
External
memory
Read Write
1
2
External device
with DACK
DACK
DREQ
: Data flow
Note:
The read/write direction is decided by the RS3-RS0 bits in the CHCRn registers. If
RS3–RS0 = 0010, the direction is as shown in case 1 (circled number above); if RS3–
RS0 = 0011, the direction is as shown in case 2. In the Electrical Characteristics section,
DACK output (read) indicates case 1, and DACK output (write) indicates case 2.
Figure 9.6 Data Flow in Single Address Mode
Two types of transfers are possible in single address mode: 1) transfers between external
devices with DACK and memory-mapped external devices, and 2) transfers between external
devices with DACK and external memory. The only transfer request for either of these is the
external request (DREQ). Figure 9.7 shows the DMA transfer timing for single address mode.
The DACK output when a transfer occurs from an external device with DACK to a memory-
mapped external device is the write waveform. The DACK output when a transfer occurs from
a memory-mapped external device to an external device with DACK is the read waveform.
The settings of the acknowledge mode (AM) bits in the channel control registers (CHCR0,
CHCR1) have no effect.
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