HD6417034 Datasheet, PDF (328/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

10.6.3 Contention between TCNT Byte Write and Increment
If an increment pulse occurs in the T2 state or T3 state of a TCNT byte write cycle, counter
writing takes priority and the byte data on the side that was previously written is not incremented.
The TCNT byte data that was not written is also not incremented and retains its previous value.
The timing is shown in figure 10.60 (which shows an increment during state T2 of a byte write
cycle to TCNTH).
TCNTH byte write cycle by CPU
T1
T2
T3
CK
Address
Internal write signal
TCNTH address
TCNT input clock
TCNTH
TCNTL
N
M
TCNT write data
X
X+1
X
Figure 10.60 Contention between TCNT Byte Write and Increment
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