HD6417034 Datasheet, PDF (348/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

11.1.4 Registers
Table 11.2 summarizes the TPC registers.
Table 11.2 TPC Registers
Name
Abbreviation R/W
Initial
Value Address*¹
Access
Size
Port B control register 1
PBCR1
R/W
H'0000 H'5FFFFCC
8, 16
Port B control register 2
PBCR2
R/W H'0000 H'5FFFFCE
8, 16
Port B data register
PBDR
R/(W)*² H'0000 H'5FFFFC2
8, 16
TPC output mode register
TPMR
R/W H'F0 H'5FFFFF0
8, 16
TPC output control register
TPCR
R/W H'FF H'5FFFFF1
8, 16
Next data enable register B NDERB
R/W H'00 H'5FFFFF2
8, 16
Next data enable register A NDERA
R/W H'00 H'5FFFFF3
8, 16
Next data register A
NDRA
R/W
H'00 H'5FFFFF5/
8, 16
H'5FFFFF7*³
Next data register B
NDRB
R/W
H'00 H'5FFFFF4/
8, 16
H'5FFFFF6*³
Notes: *1 Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Area Descriptions.
*2 Bits used for TPC output cannot be written to.
*3 These addresses change depending on the TPCR settings. When TPC output groups 0
and 1 have the same output trigger, the NDRA address is H'5FFFFF5; when their
output triggers are different, the NDRA address for group 0 is H'5FFFFF7 and the
address for group 1 is H'5FFFFF5. Likewise, when TPC output groups 2 and 3 have the
same output trigger, the NDRB address is H'5FFFFF4; when their output triggers are
different, the NDRB address for group 0 is H'5FFFFF6 and the address for group 1 is
H'5FFFFF4.
312