HD6417034 Datasheet, PDF (397/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

Bit 5: ORER Description
0
Receiving is in progress or has ended normally*¹
(Initial value)
ORER is cleared to 0 when:
• The chip is reset or enters standby mode
• Software reads ORER after it has been set to 1, then writes 0 in ORER
1
A receive overrun error occurred*²
ORER is set to 1 if reception of the next serial data ends when RDRF is set to 1
Notes: *1 Clearing the RE bit to 0 in the serial control register does not affect the ORER bit, which
retains its previous value.
*2 RDR continues to hold the data received before the overrun error, so subsequent
receive data is lost. Serial receiving cannot continue while ORER is set to 1. In
synchronous mode, serial transmitting is disabled.
• Bit 4 (Framing Error (FER)): FER indicates that data reception ended abnormally due to a
framing error in the asynchronous mode.
Bit 4: FER
0
1
Description
Receiving is in progress or has ended normally
(Initial value)
Clearing the RE bit to 0 in the serial control register does not affect the FER bit,
which retains its previous value.
FER is cleared to 0 when:
• The chip is reset or enters standby mode
• Software reads FER after it has been set to 1, then writes 0 in FER
A receive framing error occurred. When the stop bit length is two bits, only the
first bit is checked. The second stop bit is not checked. When a framing error
occurs, the SCI transfers the receive data into RDR but does not set RDRF.
Serial receiving cannot continue while FER is set to 1. In synchronous mode,
serial transmitting is also disabled.
FER is set to 1 if the stop bit at the end of receive data is checked and found to
be 0.
• Bit 3 (Parity Error (PER)): PER indicates that data reception (with parity) ended abnormally
due to a parity error in asynchronous mode.
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