HD6417034 Datasheet, PDF (381/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

12.3.4 Timing of Overflow Flag (OVF) Setting
In interval timer mode, when TCNT overflows the OVF flag in TCSR is set to 1 and an interval
timer interrupt is requested (figure 12.6).
CK
TCNT
Overflow signal
(internal signal)
H'FF H'00
OVF
Figure 12.6 Timing of OVF Setting
12.3.5 Timing of Watchdog Timer Overflow Flag (WOVF) Setting
When TCNT overflows the WOVF bit in RSTCSR is set to 1 and a WDTOVF signal is output.
When the RSTE bit is set to 1, TCNT overflow enables an internal reset signal to be generated for
the entire chip (figure 12.7).
CK
TCNT
Overflow signal
(internal signal)
H'FF H'00
WOVF
Figure 12.7 Timing of WOVF Bit Setting and Internal Reset
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