HD6417034 Datasheet, PDF (314/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

10.4.7 Phase Counting Mode
Phase counting mode detects the phase differential of two external clock inputs (TCLKA and
TCLKB) and increments or decrements TCNT2. When phase counting mode is set, the TCLKA
and TCLKB pins become external clock input pins, regardless of the settings of the TPSC2–
TPSC0 bits in TCR2 or the CKEG1 and CKEG0 bits. TCNT2 also becomes an up/down-counter.
Since the TCR2 CCLR1/CCLR0 bits, TIOR2, TIER2, TSR2, GRA2, and GRB2 are all enabled,
input capture and compare match functions and interrupt sources can be used. Phase counting is
available only for channel 2.
Procedure for Selecting Phase Counting Mode: Figure 10.42 shows the procedure for selecting
phase counting mode.
1. Set the MDF bit in the timer mode register (TMDR) to 1 to select phase counting mode.
2. Select the flag set conditions using the FDIR bit in TMDR.
3. Set the STR2 bit in the timer start register (TSTR) to 1 to start the count.
Phase counting mode
Select phase counting mode (1)
Select flag setting condition (2)
Start counting
(3)
Phase counting mode
Figure 10.42 Procedure for Selecting Phase Counting Mode
Phase Counting Operation: Figure 10.43 shows an example of phase counting mode operation.
Table 10.16 lists the up-counting and down-counting conditions for TCNT2. The ITU counts on
both rising and falling edges of TCLKA and TCLKB. The phase differential and overlap of
TCLKA and TCLKB must be 1.5 cycles or more and the pulse width must be 2.5 cycles or more.
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