HD6417034 Datasheet, PDF (7/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

Organization of This Manual
Table 1 describes how this manual is organized. Figure 1 shows the relationships between the
sections within this manual.
Table 1 Manual Organization
Category
Overview
CPU
Operating
Modes
Internal
Modules
Clock
Buses
Timers
Data
Processing
Section Title
1. Overview
2. CPU
Abbrevi-
ation
—
CPU
3. Operating Modes —
Contents
Features, internal block diagram, pin
layout, pin functions
Register configuration, data structure.
instruction features, instruction types,
instruction lists
MCU mode, PROM mode
4. Exception
Handling
5. Interrupt
Controller
6. User Break
Controller
7. Clock Pulse
Generator
8. Bus State
Controller
—
INTC
UBC
CPG
BSC
9. Direct Memory DMAC
Access
Controller
10. 16-Bit Integrated ITU
Timer Pulse Unit
11. Programmable
Timing Pattern
Controller
TPC
12. Watchdog Timer WDT
13. Serial
SCI
Communication
Interface
14. A/D Converter A/D
Resets, address errors, interrupts, trap
instructions, illegal instructions
NMI interrupts, user break interrupts, IRQ
interrupts, on-chip module interrupts
Break address and break bus cycle
selection
Crystal pulse generator, duty correction
circuit
Division of memory space, DRAM
interface, refresh, wait state control, parity
control
Auto request, external request, on-chip
peripheral module request, cycle steal
mode, burst mode
Waveform output mode, input capture
function, counter clear function, buffer
operation, PWM mode, complementary
PWM mode, reset synchronized mode,
synchronized operation, phase counting
mode, compare match output mode
Compare match output triggers, non-
overlap operation
Watchdog timer mode, interval timer mode
Asynchronous mode, synchronous mode,
multiprocessor communication function
Single mode, scan mode, activation by
external trigger