HD6417034 Datasheet, PDF (274/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

10.2.5 Timer Output Control Register (TOCR)
The timer output control register (TOCR) is an eight-bit read/write register that inverts the output
level in complementary PWM mode/reset-synchronized PWM mode. Setting bits OLS3 and OLS4
is valid only in complementary PWM mode and reset-synchronized PWM mode. In other output
situations, these bits are ignored. TOCR is initialized to H'FF or H'7F by a reset and in standby
mode.
Bit: 7
6
5
4
3
2
1
0
Bit name: —
—
—
—
—
—
OLS4 OLS3
Initial value: *
1
1
1
1
1
1
1
R/W: —
—
—
—
—
—
R/W R/W
Note: * Undefined
• Bits 7–2 (Reserved): Bit 7 is read as undefined. Bits 6–2 are always read as 1. The write value
to bit 7 should be 0 or 1. The write value to bits 6–2 should always be 1.
• Bit 1 (Output Level Select 4 (OLS4)): OLS4 selects the output level for complementary PWM
mode or reset-synchronized PWM mode.
Bit 1: OLS4
0
1
Description
TIOCA3, TIOCA4, and TIOCB4 are inverted and output
TIOCA3, TIOCA4, and TIOCB4 are output directly
(Initial value)
• Bit 0 (Output Level Select 3 (OLS3)): OLS3 selects the output level for complementary PWM
mode or reset-synchronized PWM mode.
Bit 0: OLS3
0
1
Description
TIOCB3, TOCXA4, and TOCXB4 are inverted and output
TIOCB3, TOCXA4, and TOCXB4 are output directly (Initial value)
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