HD6417034 Datasheet, PDF (198/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

8.8 Warp Mode
In warp mode, an external write cycle or DMA single address mode transfer cycle and an internal
access cycle (read/write to on-chip memory or on-chip supporting modules) operate independently
and in parallel. Warp mode is entered by setting the warp mode bit (WARP) in BCR to 1. This
allows the chip to be operated at high speed.
When, in warp mode, an external write cycle or DMA single address mode transfer cycle
continues for at least 2 states and there is an internal access, only the external write cycle will be
performed in the initial state. The external write cycle and internal access cycle will be performed
in parallel from the next state on, without waiting for the end of the external write cycle. Figure
8.34 shows the timing when an access to an on-chip supporting module and an external write cycle
are performed in parallel.
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