HD6417034 Datasheet, PDF (196/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

A high-level duty of 35% or 50% can be selected for the RD signal using the RD duty bit
(RDDTY) in BCR. When RDDTY is 1, the high-level duty is 35% of the T3 or Tw state,
lengthening the access time for external devices.
8.6.2 Wait State Control
When the address/data multiplexed I/O space is accessed, the WAIT pin input signal is sampled
and a wait state inserted whenever a low level is detected, regardless of the WCR setting. Figure
8.33 shows an example in which a WAIT signal causes one wait state to be inserted.
Tw
T1
T2
T3
(wait state)
T4
CK
A21–A0
CS
AH
RD
Read
AD15–AD0
Address
Data (input)
WRH, WRL
Write
AD15–AD0
Address
Data (output)
WAIT
Figure 8.33 Wait State Timing For Address/Data Multiplexed I/O Space Access
8.6.3 Byte Access Control
The byte access control signals when the address/data multiplexed I/O space is being accessed are
of two types (WRH, WRL, A0, or WR, HBS, LBS), just as for byte access control of external
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