HD6417034 Datasheet, PDF (680/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

Table A.77 Register Status in Reset and Power-Down States (cont)
Reset State
Power-Down State
Category
Abbreviation Power On Manual
Standby Sleep
16-bit integrated timer pulse TSTR
unit (ITU)
TSNC
Initialized Initialized Initialized Held
TMDA, TMDB
TCNT0–TCNT4
GRA0–GRA4,
GRB0–GRB4
BRA3, BRA4.
BRB3, BRB4
TCR0–TCR4
TIOR0–TIOR4
TIER0–TIER4
TSR0–TSR4
Programmable timing
pattern controller (TPC)
TPMR
TPCR
Initialized Initialized Held
Held
NDERA,NDERB
NDRA, NDRB
Watchdog timer (WDT)
TCNT
Initialized Initialized Held
Held
TCSR
*¹
RSTCR*²
Initialized
Serial communication
interface (SCI)
SMR
BRR
Initialized Initialized Initialized Held
SCR
TDR
TSR
Held
SSR
Initialized
RDR
RSR
Held
Notes: *1 Bits 7–5 (OVF, WT/IT, TME) are initialized, bits 2–0 (CKS2–CKS0) are held.
*2 Not initialized in the case of a reset by the WDT.
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