HD6417034 Datasheet, PDF (626/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

A.2.26 DMA Transfer Count Registers 0–3 (TCR0–TCR3)
DMAC
• Start Address: H'5FFFF4A (channel 0), H'5FFFF5A (channel 1), H'5FFFF6A (channel 2),
H'5FFFF7A (channel 3)
• Bus Width: 16/32
Register Overview:
Bit: 15
14
13
12
11
10
9
8
Bit name:
Initial value: *
*
*
*
*
*
*
*
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
Bit name:
Initial value: *
*
*
*
*
*
*
*
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Note: * Undetermined
Table A.27 TCR0–TCR3 Bit Functions
Bit
15–0
Bit name
(Specifies number of DMA
transfers)
Description
Specifies the number of DMA transfers (bytes or
words). During DMA transfer, indicates the number of
transfers remaining.
590