HD6417034 Datasheet, PDF (150/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

• Bits 14 and 13 (Long Wait Insertion in Areas 0 and 2, Bits 1, 0 (A02LW1 and A02LW0)):
A02LW1 and A02LW0 select the long wait states to be inserted (1–4 states) when accessing
external memory space of areas 0 and 2.
Bit 14: A02LW1
0
1
Bit 13: A02LW0
0
1
0
1
Description
1 state inserted
2 states inserted
3 states inserted
4 states inserted
(Initial value)
• Bits 12 and 11 (Long Wait Insertion in Area 6, Bits 1, 0 (A6LW1 and A6LW0)): A6LW1 and
A6LW0 select the long wait states to be inserted (1–4 states) when accessing external memory
space of area 6.
Bit 12: A6LW1
0
1
Bit 11: A6LW0
0
1
0
1
Description
1 state inserted
2 states inserted
3 states inserted
4 states inserted
(Initial value)
• Bits 10–0 (Reserved): These bits are always read as 0. The write value should always be 0.
8.2.5 DRAM Area Control Register (DCR)
The DRAM area control register (DCR) is a 16-bit read/write register that selects the type of
DRAM control signal, the number of precharge cycles, the burst operation mode, and the use of
address multiplexing. DCR settings are valid only when the DRAME bit in BCR is set to 1. It is
initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby
mode.
Bit:
Bit name:
Initial value:
R/W:
15
CW2
0
R/W
14
RASD
0
R/W
13
TPC
0
R/W
12
11
10
9
8
BE CDTY MXE MXC1 MXC0
0
0
0
0
0
R/W R/W R/W R/W R/W
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