HD6417034 Datasheet, PDF (49/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

Table 1.3 Pin Functions (cont)
Type
Pin No.
Symbol (FP-112)
Bus control WAIT 56
(cont)
RAS 54
CASH 49
CASL 51
RD
59
WRH 58
WRL 57
CS0–
CS7
AH
48–51,
53–56
63
HBS,
LBS
23, 58
WR
57
DMAC
DREQ0, 67, 69
DREQ1
DACK0, 66, 68
DACK1
16-bit
TIOCA0, 53, 55
integrated TIOCB0
timer pulse _{TIOCA1, 64, 65}
unit (ITU) _TIOCB1
TIOCA2, 97, 98
TIOCB2
TIOCA3, 100, 101
TIOCB3
Pin No.
(TFP-120) I/O Name and Function
59
I Wait: Requests the insertion of wait states
(T_W) into the bus cycle when the external
address space is accessed.
57
O Row address strobe: DRAM row-address
strobe timing signal.
52
O Column address strobe high: DRAM column-
address strobe timing signal. Output to access
the upper eight data bits.
54
O Column address strobe low: DRAM column-
address strobe timing. Output to access the
lower eight data bits.
64
O Read: Indicates reading of data from an
external device.
63
O Upper write: Indicates write access to the
upper eight bits of an external device.
62
O Lower write: Indicates write access to the
lower eight bits of an external device.
51–54,
56–59
O Chip select 0–7: Chip select signals for
accessing external memory and devices.
68
O Address hold: Address hold timing signal for a
device using a multiplexed address/data bus.
24, 63
O Upper/lower byte strobe: Upper and lower
byte strobe signals. (Also used as WRH and
A0.)
62
O Write: Brought low during write access. (Also
used as WRL.)
72, 74
I DMA transfer request (channels 0 and 1):
Input pins for external DMA transfer requests.
71, 73
O DMA transfer acknowledge (channels 0 and
1): Indicates that DMA transfer is
acknowledged.
56, 58
I/O ITU input capture/output compare (channel 0):
Input capture or output compare pins.
69, 70
I/O ITU input capture/output compare (channel 1):
Input capture or output compare pins.
103, 105 I/O ITU input capture/output compare (channel 2):
Input capture or output compare pins.
107, 108 I/O ITU input capture/output compare (channel 3):
Input capture or output compare pins.
13