HD6417034 Datasheet, PDF (26/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

8.2.2 Wait State Control Register 1 (WCR1)................................................................ 109
8.2.3 Wait State Control Register 2 (WCR2)................................................................ 111
8.2.4 Wait State Control Register 3 (WCR3)................................................................ 113
8.2.5 DRAM Area Control Register (DCR).................................................................. 114
8.2.6 Refresh Control Register (RCR) .......................................................................... 117
8.2.7 Refresh Timer Control/Status Register (RTCSR) ................................................ 118
8.2.8 Refresh Timer Counter (RTCNT) ........................................................................ 120
8.2.9 Refresh Time Constant Register (RTCOR).......................................................... 120
8.2.10 Parity Control Register (PCR).............................................................................. 121
8.2.11 Notes on Register Access ..................................................................................... 123
8.3 Address Space Subdivision................................................................................................ 124
8.3.1 Address Spaces and Areas.................................................................................... 124
8.3.2 Bus Width............................................................................................................. 126
8.3.3 Chip Select Signals (CS0–CS7)............................................................................ 126
8.3.4 Shadows................................................................................................................ 127
8.3.5 Area Descriptions ................................................................................................. 129
8.4 Accessing External Memory Space ................................................................................... 136
8.4.1 Basic Timing ........................................................................................................ 136
8.4.2 Wait State Control ................................................................................................ 138
8.4.3 Byte Access Control ............................................................................................. 141
8.5 DRAM Interface Operation ............................................................................................... 142
8.5.1 DRAM Address Multiplexing .............................................................................. 142
8.5.2 Basic Timing ........................................................................................................ 144
8.5.3 Wait State Control ................................................................................................ 146
8.5.4 Byte Access Control ............................................................................................. 148
8.5.5 DRAM Burst Mode .............................................................................................. 150
8.5.6 Refresh Control .................................................................................................... 155
8.6 Address/Data Multiplexed I/O Space Access.................................................................... 159
8.6.1 Basic Timing ........................................................................................................ 159
8.6.2 Wait State Control ................................................................................................ 160
8.6.3 Byte Access Control ............................................................................................. 160
8.7 Parity Check and Generation ............................................................................................. 161
8.8 Warp Mode........................................................................................................................ 162
8.9 Wait State Control ............................................................................................................. 163
8.10 Bus Arbitration .................................................................................................................. 166
8.10.1 Operation of Bus Arbitration................................................................................ 167
8.10.2 BACK Operation.................................................................................................. 168
8.11 Usage Notes ....................................................................................................................... 169
8.11.1 Usage Notes on Manual Reset.............................................................................. 169
8.11.2 Usage Notes on Parity Data Pins DPH and DPL ................................................. 172
8.11.3 Maximum Number of States from BREQ Input to Bus Release ......................... 172
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