HD6417034 Datasheet, PDF (96/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

Table 4.7 Interrupt Priority Rankings
Type
NMI
User break
IRQ and on-chip supporting
modules
Priority
16
15
0–15
Comments
Fixed and unmaskable
Fixed
Set in interrupt priority level registers A–E
(IPRA–IPRE)
4.4.3 Interrupt Exception Handling
When an interrupt is generated, the INTC ascertains the interrupt ranking. NMI is always
accepted, but other interrupts are only accepted if their ranking is higher than the ranking set in the
interrupt mask bits (I3–I0) of SR.
When an interrupt is accepted, interrupt exception handling begins. In the interrupt exception
handling sequence, the SR and PC values are pushed onto the stack, and the priority level of the
accepted interrupt is copied to the interrupt mask level bits (I3–I0) in SR. In NMI exception
handling, the priority ranking is 16 but the value 15 (H'F) is stored in I3–I0. The exception
handling routine start address for the accepted interrupt is fetched from the exception vector table
and the program branches to that address and starts executing. For further information on
interrupts, see section 5.4, Interrupt Operation.
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