EP2S180F1020C4 Datasheet, PDF (83/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Stratix II Architecture
Table 2–11. Global & Regional Clock Connections from Top Clock Pins & Enhanced PLL Outputs (Part 1
of 2)
Top Side Global & Regional
Clock Network Connectivity
Clock pins
CLK12p
CLK13p
CLK14p
CLK15p
CLK12n
CLK13n
CLK14n
CLK15n
Drivers from internal logic
GCLKDRV0
GCLKDRV1
GCLKDRV2
GCLKDRV3
RCLKDRV0
RCLKDRV1
RCLKDRV2
RCLKDRV3
RCLKDRV4
RCLKDRV5
RCLKDRV6
RCLKDRV7
Enhanced PLL 5 outputs
c0
c1
c2
c3
vvv
v
v
vvv
v
v
v
vv
v
v
v
vv
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
vvv
v
v
vvv
v
v
v
vv
v
v
v
vv
v
v
Altera Corporation
May 2007
2–65
Stratix II Device Handbook, Volume 1