EP2S180F1020C4 Datasheet, PDF (340/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Clocking
Clock Output Connections
Enhanced PLLs have outputs for eight regional clock outputs and four
global clock outputs. There is line sharing between clock pins, global and
regional clock networks and all PLL outputs. See Tables 1–18 through
1–23 and Figures 1–47 through 1–53 to validate your clocking scheme.
The Quartus II software automatically maps to regional and global clocks
to avoid any restrictions. Enhanced PLLs 5, 6, 11, and 12 drive out to
single-ended pins as shown in Table 1–23.
You can connect each fast PLL 1, 2, 3, or 4 output (C0, C1, C2, and C3) to
either a global or a regional clock. There is line sharing between clock
pins, FPLLCLK pins, global and regional clock networks, and all PLL
outputs. The Quartus II software will automatically map to regional and
global clocks to avoid any restrictions.
Figure 1–47 shows the clock input and output connections from the
enhanced PLLs.
1
EP2S15, EP2S30, and EP2SGX30 devices have only two
enhanced PLLs (5, 6), but the connectivity from these two PLLs
to the global or regional clock networks remains the same.
The EP2S60 device in the 1,020-pin package contains 12 PLLs.
EP2S60 devices in the 484-pin and 672-pin packages contain fast
PLLs 1–4 and enhanced PLLs 5 and 6.
EP2S90 devices in the 1020-pin and 1508-pin packages contain
12 PLLs. EP2S90 devices in the 484-pin and 780-pin packages
contain fast PLLs 1–4 and enhanced PLLs 5 and 6.
EP2S130 devices in the 1020-pin and 1508-pin packages contain
12 PLLs. The EP2S130 device in the 780-pin package contains
fast PLLs 1–4 and enhanced PLLs 5 and 6.
1–76
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009