EP2S180F1020C4 Datasheet, PDF (431/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

External Memory Interfaces in Stratix II and Stratix II GX Devices
Figure 3–16. DQS Configuration in Stratix II or Stratix II GX IOE
DFF
OE
(2)
DQ
Note (1)
OE Register A_OE
1
0
OR2
(3)
DFF
DQ
Logic Array
datain_h (4)
datain_l (4)
system clock
OE Register B_OE
DFF
DQ
TRI
1
Output Register A_O
0
DFF
DQ
Output Register B_O
DQS Pin (5)
combout (7)
Notes to Figure 3–16:
(1) You can use the altdqs megafunction to generate the DQS signals. You should, however, use Altera’s memory
controller IP Tool Bench to generate the data path for your memory interface. The signal names used here match
with Quartus II software naming convention.
(2) The OE signal is active low, but the Quartus II software implements this as active high and automatically adds an
inverter before OE register A_OE during compilation. In RLDRAM II and QDRII SRAM, the OE signal is always
disabled.
(3) The select line can be chosen in the altdqs megafunction.
(4) The datain_l and datain_h pins are usually connected to ground and V_CC, respectively.
(5) DQS postamble circuitry and handling is not shown in this diagram. For more information, see AN 327: Interfacing
DDR SDRAM with Stratix II Devices and AN 328: Interfacing DDR2 SDRAM with Stratix II Devices.
(6) DQS logic blocks are only available with DQS and DQSn pins.
(7) You must invert this signal before it reaches the DQ IOE. This signal is automatically inverted if you use the altdq
megafunction to generate the DQ signals. Connect this port to the inclock port in the altdq megafunction.
Altera Corporation
January 2008
3–35
Stratix II Device Handbook, Volume 2