EP2S180F1020C4 Datasheet, PDF (347/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

PLLs in Stratix II and Stratix II GX Devices
Figures 1–48 through 1–51 show the global and regional clock input and
output connections from the Stratix II fast PLLs.
Figure 1–48. Stratix II Center Fast PLLs, Clock Pin and Logic Array Signal
Connectivity to Global and Regional Clock Networks Notes (1) and (2)
Notes to Figure 1–48:
(1) The redundant connection dots facilitate stitching of the clock networks to support
the ability to drive two quadrants with the same clock.
(2) The global or regional clocks in a fast PLL's quadrant can drive the fast PLL input.
The global or regional clock input can be driven by an output from another PLL, a
pin-driven dedicated global or regional clock, or through a clock control block,
provided the clock control block is fed by an output from another PLL or a
pin-driven dedicated global or regional clock. An internally generated global
signal cannot drive the PLL.
Altera Corporation
July 2009
1–83
Stratix II Device Handbook, Volume 2