EP2S180F1020C4 Datasheet, PDF (711/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

IEEE 1149.1 (JTAG) Boundary-Scan Testing for Stratix II and Stratix II GX Devices
Using IEEE Std.
1149.1 BST
Circuitry
f
Stratix II and Stratix II GX devices have dedicated JTAG pins and the
IEEE Std. 1149.1 BST circuitry is enabled upon device power-up. Not only
can you perform BST on Stratix II and Stratix II GX FPGAs before and
after, but also during configuration. Stratix II and Stratix II GX FPGAs
support the BYPASS, IDCODE and SAMPLE instructions during
configuration without interrupting configuration. To send all other JTAG
instructions, you must interrupt configuration using the CONFIG_IO
instruction.
The CONFIG_IO instruction allows you to configure I/O buffers via the
JTAG port, and when issued, interrupts configuration. This instruction
allows you to perform board-level testing prior to configuring the
Stratix II or the Stratix II GX FPGA or you can wait for the configuration
device to complete configuration. Once configuration is interrupted and
JTAG BST is complete, you must reconfigure the part via JTAG
(PULSE_CONFIG instruction) or by pulsing nCONFIG low.
1
When you perform JTAG boundary-scan testing before
configuration, the nCONFIG pin must be held low.
The chip-wide reset (DEV_CLRn) and chip-wide output enable (DEV_OE)
pins on Stratix II and Stratix II GX devices do not affect JTAG
boundary-scan or configuration operations. Toggling these pins does not
disrupt BST operation (other than the expected BST behavior).
When you design a board for JTAG configuration of Stratix II or
Stratix II GX devices, you need to consider the connections for the
dedicated configuration pins.
For more information on using the IEEE Std.1149.1 circuitry for device
configuration, refer to the Configuring Stratix II & Stratix II GX Devices
chapter in volume 2 of the Stratix II Device Handbook or the Configuring
Stratix II & Stratix II GX Devices chapter in volume 2 of the Stratix II GX
Device Handbook.
BST for
Configured
Devices
For a configured device, the input buffers are turned off by default for
I/O pins that are set as output only in the design file. You cannot sample
on the configured device output pins with the default BSDL file when the
input buffers are turned off. You can set the Quartus II software to always
enable the input buffers on a configured device so it behaves the same as
an unconfigured device for boundary-scan testing, allowing sample
function on output pins in the design. This aspect can cause slight
increase in standby current because the unused input buffer is always on.
In the Quartus II software, do the following:
1. Choose Settings (Assignments menu).
Altera Corporation
January 2008
9–19
Stratix II Device Handbook, Volume 2