EP2S180F1020C4 Datasheet, PDF (710/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

I/O Voltage Support in JTAG Chain
Table 9–3. Supported TDO/TDI Voltage Combinations
Device
TDI Input Buffer
Power
Stratix II and
Stratix II GX
Non-Stratix II
Always V_{C C P D} (3.3V)
VCC = 3.3 V
VCC = 2.5 V
VCC = 1.8 V
VCC = 1.5 V
Stratix II and Stratix II GX TDO V_{CCI O} Voltage Level in I/O Bank 4
V_{C C I O} = 3.3 V
v (1)
v (1)
v (1), (4)
v (1), (4)
v (1), (4)
V_{C C I O} = 2.5 V
v (2)
v (2)
v (2)
v (2), (5)
v (2), (5)
V_{C C I O} = 1.8 V
v (3)
v (3)
v (3)
v
v (6)
V_{C C I O} = 1.5 V
level shifter
required
level shifter
required
level shifter
required
level shifter
required
v
Notes to Table 9–3:
(1) The TDO output buffer meets V_OH (MIN) = 2.4 V.
(2) The TDO output buffer meets V_OH (MIN) = 2.0 V.
(3) An external 250- pull-up resistor is not required, but recommended if signal levels on the board are not optimal.
(4) Input buffer must be 3.3-V tolerant.
(5) Input buffer must be 2.5-V tolerant.
(6) Input buffer must be 1.8-V tolerant.
Figure 9–13. JTAG Chain of Mixed Voltages
Must be 3.3 V Tolerant.
Tester
TDI
3.3 V
V_CCIO
2.5 V
V_CCIO
TDO _Level
Shifter
1.5 V
V_CCIO
1.8 V
V_CCIO
Shift TDO to
level accepted
by tester if
necessary.
Must be
1.8 V tolerant.
Must be
2.5 V tolerant.
9–18
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008