EP2S180F1020C4 Datasheet, PDF (197/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

DC & Switching Characteristics
IOE Programmable Delay
See Tables 5–69 and 5–70 for IOE programmable delay.
Table 5–69. Stratix II IOE Programmable Delay on Column Pins Note (1)
Parameter
Minimum
-3 Speed
-4 Speed
-5 Speed
Timing (2) Grade (3)
Grade
Grade
Paths Affected
Available
Settings
Min
Max
Min
Max
Min
Max
Min
Max
Offset Offset Offset Offset Offset Offset Offset Offset
(ps) (ps) (ps) (ps) (ps) (ps) (ps) (ps)
Input delay from Pad to I/O
8
pin to internal dataout to logic
cells
array
Input delay from Pad to I/O input 64
pin to input
register
register
Delay from
I/O output
2
output register register to pad
to output pin
Output enable t_{X Z} , t_{Z X}
2
pin delay
0 1,696 0 2,881 0 3,313 0 3,860
0 1,781 0 3,025
0 1,955 0 3,275 0 3,766 0 4,388
0 2,053 0 3,439
0 316 0 500 0 575 0 670
0 332 0 525
0 305 0 483 0 556 0 647
0 320 0 507
Notes to Table 5–69:
(1) The incremental values for the settings are generally linear. For the exact delay associated with each setting, use the
latest version of the Quartus II software.
(2) The first number is the minimum timing parameter for industrial devices. The second number is the minimum
timing parameter for commercial devices.
(3) The first number applies to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices. The second number
applies to -3 speed grade EP2S130 and EP2S180 devices.
Altera Corporation
April 2011
5–51
Stratix II Device Handbook, Volume 1