EP2S180F1020C4 Datasheet, PDF (226/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Duty Cycle Distortion
Table 5–80. Maximum DCD for Non-DDIO Output on Row I/O Pins (Part 2
of 2) Note (1)
Row I/O Output
Standard
1.8 V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
1.8-V HSTL Class I
1.5-V HSTL Class I
LVDS/
HyperTransport
technology
Maximum DCD for Non-DDIO Output
-3 Devices
-4 & -5 Devices
Unit
180
180
ps
165
195
ps
115
145
ps
95
125
ps
55
85
ps
80
100
ps
85
115
ps
55
80
ps
Note to Table 5–80:
(1) The DCD specification is based on a no logic array noise condition.
Here is an example for calculating the DCD as a percentage for a
non-DDIO output on a row I/O on a -3 device:
If the non-DDIO output I/O standard is SSTL-2 Class II, the maximum
DCD is 95 ps (see Table 5–80). If the clock frequency is 267 MHz, the clock
period T is:
T = 1/ f = 1 / 267 MHz = 3.745 ns = 3745 ps
To calculate the DCD as a percentage:
(T/2 – DCD) / T = (3745ps/2 – 95ps) / 3745ps = 47.5% (for low
boundary)
(T/2 + DCD) / T = (3745ps/2 + 95ps) / 3745ps = 52.5% (for high
boundary)
5–80
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011