EP2S180F1020C4 Datasheet, PDF (502/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Clocking
Figure 5–18. Bit Order for One Channel of Differential Data
Transmitter Channel
Operation (x8 Mode)
tx_outclock
tx_out
Previous Cycle
Current Cycle
Next Cycle
X XX X X X X X 7 6 5 4 3 2 1 0 XX X XX X X X
MSB
LSB
Receiver Channel
Operation (x4 Mode)
rx_inclock
rx_in
3 2 1 0 XX X XX X XX X X X X
rx_outclock
rx_out [3..0]
XXXX
XXXX
XXXX
3210
Receiver Channel
Operation (x8 Mode)
rx_inclock
rx_in
7 6 5 4 3 2 1 0 X X X XX X X X XX X XX X X X XXX X X X X X
rx_outclock
rx_out [7..0]
XXXXXXXX
XXXXXXXX
XXXX7654
3210XXXX
5–18
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008