EP2S180F1020C4 Datasheet, PDF (425/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

External Memory Interfaces in Stratix II and Stratix II GX Devices
1 The input reference clock for the DQS phase-shift circuitry on
the top side of the device can come from CLK[15..12]p or
PLL 5. The input reference clock for the DQS phase-shift
circuitry on the bottom side of the device can come from
CLK[7..4]p or PLL 6.
Figure 3–11. Simplified Diagram of the DQS Logic Block Note (1)
Notes to Figure 3–11:
(1) All features of the DQS logic block are accessible from the altdqs megafunction in the Quartus II software. You
should; however, use Altera’s memory controller IP Tool Bench to generate the data path for your memory interface.
(2) The input reference clock for the DQS phase-shift circuitry on the top side of the device can come from
CLK[15..12]p or PLL 5. The input reference clock for the DQS phase-shift circuitry on the top side of the device
can come from CLK[7..4]p or PLL 6.
(3) This register is one of the DQS IOE input registers.
Altera Corporation
January 2008
3–29
Stratix II Device Handbook, Volume 2