EP2S180F1020C4 Datasheet, PDF (570/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Fast Passive Parallel Configuration
entered user mode. When initialization is complete, the device enters user
mode. In user-mode, the user I/O pins no longer have weak pull-up
resistors and function as assigned in your design.
To ensure DCLK and DATA[7..0] are not left floating at the end of
configuration, the MAX II device must drive them either high or low,
whichever is convenient on your board. The DATA[7..0] pins are
available as user I/O pins after configuration. When you select the FPP
scheme in the Quartus II software, as a default, these I/O pins are
tri-stated in user mode. To change this default option in the Quartus II
software, select the Pins tab of the Device & Pin Options dialog box.
The configuration clock (DCLK) speed must be below the specified
frequency to ensure correct configuration. No maximum DCLK period
exists, which means you can pause configuration by halting DCLK for an
indefinite amount of time.
1 If you are using the Stratix II or Stratix II GX decompression
and/or design security feature and need to stop DCLK, it can
only be stopped three clock cycles after the last data byte was
latched into the Stratix II or Stratix II GX device.
By stopping DCLK, the configuration circuit allows enough clock cycles to
process the last byte of latched configuration data. When the clock
restarts, the MAX II device must provide data on the DATA[7..0] pins
prior to sending the first DCLK rising edge.
If an error occurs during configuration, the device drives its nSTATUS pin
low, resetting itself internally. The low signal on the nSTATUS pin also
alerts the MAX II device that there is an error. If the Auto-restart
configuration after error option (available in the Quartus II software
from the General tab of the Device & Pin Options (dialog box) is turned
on, the device releases nSTATUS after a reset time-out period (maximum
of 100 µs). After nSTATUS is released and pulled high by a pull-up
resistor, the MAX II device can try to reconfigure the target device
without needing to pulse nCONFIG low. If this option is turned off, the
MAX II device must generate a low-to-high transition (with a low pulse
of at least 2 µs) on nCONFIG to restart the configuration process.
The MAX II device can also monitor the CONF_DONE and INIT_DONE
pins to ensure successful configuration. The CONF_DONE pin must be
monitored by the MAX II device to detect errors and determine when
programming completes. If all configuration data is sent, but the
CONF_DONE or INIT_DONE signals have not gone high, the MAX II
device will reconfigure the target device.
7–18
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008