EP2S180F1020C4 Datasheet, PDF (369/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

TriMatrix Embedded Memory Blocks in Stratix II and Stratix II GX Devices
Figure 2–3. Stratix II and Stratix II GX Address Clock Enable During Read Cycle Waveform
inclock
rdaddress
a0
a1
a2
a3
a4
a5
a6
rden
addressstall
latched address
(inside memory) ^an
a0
a1
a4
a5
q (synch) doutn-1 doutn
dout0
dout1
dout1
dout1
dout4
q (asynch) doutn
dout0
dout1
dout1
dout1
dout4
dout5
Figure 2–4. Stratix II and Stratix II GX Address Clock Enable During Write Cycle Waveform
inclock
wraddress
data
wren
addressstall
latched address
(inside memory)
contents at a0
contents at a1
contents at a2
contents at a3
contents at a4
contents at a5
a0
a1
00
01
an
a0
XX
XX
a2
a3
02
03
a1
00
01
02
XX
XX
XX
XX
a4
a5
a6
04
05
06
a4
a5
03
04
05
Memory Modes
Stratix II and Stratix II GX TriMatrix memory blocks include input
registers that synchronize writes, and output registers to pipeline data to
improve system performance. All TriMatrix memory blocks are fully
synchronous, meaning that all inputs are registered, but outputs can be
either registered or unregistered.
Altera Corporation
January 2008
2–9
Stratix II Device Handbook, Volume 2