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EP2S180F1020C4 Datasheet, PDF (256/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1 | |||
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Contents
Stratix II Device Handbook, Volume 2
Remote System Upgrade Registers .............................................................................................. 8â15
Remote System Upgrade State Machine ..................................................................................... 8â19
User Watchdog Timer .................................................................................................................... 8â20
Interface Signals between Remote System Upgrade Circuitry and FPGA Logic Array ...... 8â21
Remote System Upgrade Pin Descriptions ................................................................................. 8â23
Quartus II Software Support .............................................................................................................. 8â24
altremote_update Megafunction .................................................................................................. 8â24
Remote System Upgrade Atom .................................................................................................... 8â28
System Design Guidelines .................................................................................................................. 8â28
Remote System Upgrade With Serial Configuration Devices ................................................. 8â29
Remote System Upgrade With a MAX II Device or Microprocessor and Flash Device ...... 8â29
Remote System Upgrade with Enhanced Configuration Devices .......................................... 8â30
Conclusion ............................................................................................................................................ 8â31
Referenced Documents ....................................................................................................................... 8â31
Document Revision History ............................................................................................................... 8â32
Chapter 9. IEEE 1149.1 (JTAG) Boundary-Scan Testing for Stratix II and Stratix II GX
Devices
Introduction ............................................................................................................................................ 9â1
IEEE Std. 1149.1 BST Architecture ...................................................................................................... 9â2
IEEE Std. 1149.1 Boundary-Scan Register .......................................................................................... 9â4
Boundary-Scan Cells of a Stratix II or Stratix II GX Device I/O Pin ........................................ 9â5
IEEE Std. 1149.1 BST Operation Control ............................................................................................ 9â7
SAMPLE/PRELOAD Instruction Mode ..................................................................................... 9â11
Capture Phase ................................................................................................................................. 9â12
Shift and Update Phases ................................................................................................................ 9â12
EXTEST Instruction Mode ............................................................................................................ 9â13
Capture Phase ................................................................................................................................. 9â14
Shift and Update Phases ................................................................................................................ 9â14
BYPASS Instruction Mode ............................................................................................................ 9â15
IDCODE Instruction Mode ........................................................................................................... 9â16
USERCODE Instruction Mode ..................................................................................................... 9â16
CLAMP Instruction Mode ............................................................................................................ 9â17
HIGHZ Instruction Mode ............................................................................................................. 9â17
I/O Voltage Support in JTAG Chain ................................................................................................ 9â17
Using IEEE Std. 1149.1 BST Circuitry ............................................................................................... 9â19
BST for Configured Devices ............................................................................................................... 9â19
Disabling IEEE Std. 1149.1 BST Circuitry ......................................................................................... 9â20
Guidelines for IEEE Std. 1149.1 Boundary-Scan Testing ............................................................... 9â20
Boundary-Scan Description Language (BSDL) Support ................................................................ 9â21
Conclusion ............................................................................................................................................ 9â21
References ............................................................................................................................................. 9â22
Referenced Documents ....................................................................................................................... 9â22
Document Revision History ............................................................................................................... 9â22
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Altera Corporation
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