EP2S180F1020C4 Datasheet, PDF (498/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Clocking
Clocking
The fast PLLs feed in to the differential receiver and transmitter channels
through the LVDS/DPA clock network. The center fast PLLs can
independently feed the banks above and below them. The corner PLLs
can feed only the banks adjacent to them. Figures 5–13 and 5–14 show the
LVDS and DPA clock networks of the Stratix II devices.
Figure 5–13. Fast PLL and LVDS/DPA Clock for EP2S15, EP2S30, and EP2S60 Devices Note (1)
LVDS DPA
4 ^{Clock Clock}
Quadrant
Quadrant
DPA LVDS
Clock Clock ₄
4
2
Fast
PLL 1
2
Fast
PLL 2
4
LVDS DPA
4 Clock Clock
Quadrant
Quadrant
Fast
PLL 4
Fast
PLL 3
4
2
2
4
DPA LVDS
Clock Clock 4
Note to Figure 5–13:
(1) Figure 5–13 applies to EP2S60 devices in the 484 and 672 pin packages.
5–14
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008