EP2S180F1020C4 Datasheet, PDF (657/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Configuring Stratix II and Stratix II GX Devices
Table 7–24 describes the dedicated JTAG pins. JTAG pins must be kept
stable before and during configuration to prevent accidental loading of
JTAG instructions. The TDI, TMS, and TRST have weak internal pull-up
resistors (typically 25 k) while TCK has a weak internal pull-down
resistor. If you plan to use the SignalTap embedded logic array analyzer,
you need to connect the JTAG pins of the Stratix II or Stratix II GX device
to a JTAG header on your board.
Table 7–24. Dedicated JTAG Pins (Part 1 of 2)
Pin Name User Mode Pin Type
Description
TDI
N/A
Input Serial input pin for instructions as well as test and programming data. Data
is shifted in on the rising edge of TCK. The TDI pin is powered by the 3.3-V
V_{C C P D} supply.
TDO
If the JTAG interface is not required on the board, the JTAG circuitry can be
disabled by connecting this pin to V_{C C}.
N/A
Output Serial data output pin for instructions as well as test and programming data.
Data is shifted out on the falling edge of TCK. The pin is tri-stated if data is
not being shifted out of the device. The TDO pin is powered by V_{C C I O} in I/O
bank 4. For recommendations on connecting a JTAG chain with multiple
voltages across the devices in the chain, refer to the IEEE 1149.1 (JTAG)
Boundary Scan Testing in Stratix II & Stratix II GX Devices chapter in volume
2 of the Stratix II Handbook or the IEEE 1149.1 (JTAG) Boundary Scan
Testing in Stratix II & Stratix II GX Devices chapter in volume 2 of the
Stratix II GX Device Handbook.
TMS
If the JTAG circuitry is not used, leave the TDO pin unconnected.
N/A
Input Input pin that provides the control signal to determine the transitions of the
TAP controller state machine. Transitions within the state machine occur on
the rising edge of TCK. Therefore, TMS must be set up before the rising
edge of TCK. TMS is evaluated on the rising edge of TCK. The TMS pin is
powered by the 3.3-V V_{C C P D} supply.
If the JTAG interface is not required on the board, the JTAG circuitry can be
disabled by connecting this pin to V_CC.
Altera Corporation
January 2008
7–105
Stratix II Device Handbook, Volume 2