EP2S180F1020C4 Datasheet, PDF (627/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Configuring Stratix II and Stratix II GX Devices
f
1 You can hold nConfig low in order to stop device
configuration.
The value of the weak pull-up resistors on the I/O pins that are on before
and during configuration can be found in the DC & Switching
Characteristics chapter in volume 1 of the Stratix II Device Handbook and
the DC & Switching Characteristics chapter in volume 1 of the Stratix II GX
Device Handbook.
The configuration cycle consists of three stages: reset, configuration and
initialization. While nCONFIG or nSTATUS are low, the device is in reset.
To initiate configuration, the microprocessor must generate a low-to-high
transition on the nCONFIG pin.
1
To begin configuration, power the V_CCINT, V_CCIO, and V_CCPD
voltages (for the banks where the configuration and JTAG pins
reside) to the appropriate voltage levels.
When nCONFIG goes high, the device comes out of reset and releases the
open-drain nSTATUS pin, which is then pulled high by an external 10-k
pull-up resistor. Once nSTATUS is released the device is ready to receive
configuration data and the configuration stage begins. When nSTATUS is
pulled high, the microprocessor should then assert the target device’s
nCS pin low and/or CS pin high. Next, the microprocessor places an 8-bit
configuration word (one byte) on the target device’s DATA[7..0] pins
and pulses the nWS pin low.
On the rising edge of nWS, the target device latches in a byte of
configuration data and drives its RDYnBSY signal low, which indicates it
is processing the byte of configuration data. The microprocessor can then
perform other system functions while the Stratix II or Stratix II GX device
is processing the byte of configuration data.
During the time RDYnBSY is low, the Stratix II or Stratix II GX device
internally processes the configuration data using its internal oscillator
(typically 100 MHz). When the device is ready for the next byte of
configuration data, it will drive RDYnBSY high. If the microprocessor
senses a high signal when it polls RDYnBSY, the microprocessor sends the
next byte of configuration data to the device.
Alternatively, the nRS signal can be strobed low, causing the RDYnBSY
signal to appear on DATA7. Because RDYnBSY does not need to be
monitored, this pin doesn’t need to be connected to the microprocessor.
Do not drive data onto the data bus while nRS is low because it will cause
contention on the DATA7 pin. If you are not using the nRS pin to monitor
configuration, it should be tied high.
Altera Corporation
January 2008
7–75
Stratix II Device Handbook, Volume 2