EP2S180F1020C4 Datasheet, PDF (495/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices
are equally divided, giving a 45-degree resolution. Figure 5–10 shows the
possible phase relationships between the DPA clocks and the incoming
serial data.
Figure 5–10. DPA Clock Phase to Data Bit Relationship
rx_in
D0
D1
D2
D3
D4
Dn
0˚
45˚
90˚
135˚
180˚
225˚
270˚
315˚
0.125T_vco
T_vco
Each DPA block continuously monitors the phase of the incoming data
stream and selects a new clock phase if needed. The selection of a new
clock phase can be prevented by the optional RX_DPLL_HOLD port, which
is available for each channel.
The DPA block requires a training pattern and a training sequence of at
least 256 repetitions of the training pattern. The training pattern is not
fixed, so you can use any training pattern with at least one transition on
each channel. An optional output port, RX_DPA_LOCKED, is available to
the internal logic, to indicate when the DPA block has settled on the
closest phase to the incoming data phase. The RX_DPA_LOCKED
de-asserts, depending on what is selected in the Quartus II MegaWizard
Plug-In, when either a new phase is selected, or when the DPA has moved
two phases in the same direction. The data may still be valid even when
the RX_DPA_LOCKED is deasserted. Use data checkers to validate the data
when RX_DPA_LOCKED is deasserted.
An independent reset port, RX_RESET, is available to reset the DPA
circuitry. The DPA circuit must be retrained after reset.
Altera Corporation
January 2008
5–11
Stratix II Device Handbook, Volume 2