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EP2S180F1020C4 Datasheet, PDF (393/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1 | |||
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TriMatrix Embedded Memory Blocks in Stratix II and Stratix II GX Devices
Read-During-
Write Operation
at the Same
Address
The âSame-Port Read-During-Write Modeâ on page 2â33 and âMixed-
Port Read-During-Write Modeâ on page 2â34 sections describe the
functionality of the various RAM configurations when reading from an
address during a write operation at that same address. There are two
read-during-write data flows: same-port and mixed-port. Figure 2â20
shows the difference between these flows.
Figure 2â20. Stratix II and Stratix II GX Read-During-Write Data Flow
Port A
data in
Port B
data in
Port A
data out
Port B
data out
Mixed-port
data flow
Same-port
data flow
Same-Port Read-During-Write Mode
For read-during-write operation of a single-port RAM or the same port of
a true dual-port RAM, the new data is available on the rising edge of the
same clock cycle on which it was written. This behavior is valid on all
memory block sizes. Figure 2â21 shows a sample functional waveform.
When using byte enables in true dual-port RAM mode, the outputs for
the masked bytes on the same port are unknown (refer to Figure 2â1 on
page 2â7). The non-masked bytes are read out as shown in Figure 2â21.
Altera Corporation
January 2008
2â33
Stratix II Device Handbook, Volume 2
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