EP2S180F1020C4 Datasheet, PDF (469/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Altera Corporation
January 2008
Selectable I/O Standards in Stratix II and Stratix II GX Devices
Table 4–6 shows the list of output standards that support on-chip series
termination with calibration.
Table 4–6. Selectable I/O Drivers with On-Chip Series Termination with
Calibration
I/O Standard
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVTTL
2.5-V LVCMOS
1.8-V LVTTL
1.8-V LVCMOS
1.5 LVTTL
1.5 LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.2-V HSTL (1)
On-Chip Series Termination Setting
(Column I/O)
Unit
50

25

50

25

50

25

50

25

50

25

50

25

50

50

50

25

50

25

50

25

50

50

Note to Table 4–6:
(1) 1.2-V HSTL is only supported in I/O banks 4,7, and 8.
On-Chip Parallel Termination with Calibration
Stratix II and Stratix II GX devices support on-chip parallel termination
with calibration in column I/Os in top and bottom banks. Every column
I/O buffer consists of a group of transistors in parallel. Each transistor can
be individually enabled or disabled. The on-chip parallel termination
calibration circuit compares the total impedance of the transistor group to
4–31
Stratix II Device Handbook, Volume 2