EP2S180F1020C4 Datasheet, PDF (679/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Remote System Upgrades with Stratix II and Stratix II GX Devices
Remote System Upgrade State Machine
The remote system upgrade control and update registers have identical
bit definitions, but serve different roles (see Table 8–3 on page 8–15).
While both registers can only be updated when the FPGA is loaded with
a factory configuration image, the update register writes are controlled by
the user logic, and the control register writes are controlled by the remote
system upgrade state machine.
In factory configurations, the user logic should send the AnF bit (set high),
the page address, and watchdog timer settings for the next application
configuration bit to the update register. When the logic array
configuration reset (RU_nCONFIG) goes high, the remote system upgrade
state machine updates the control register with the contents of the update
register and initiates system reconfiguration from the new application
page.
In the event of an error or reconfiguration trigger condition, the remote
system upgrade state machine directs the system to load a factory or
application configuration (page zero or page one, based on mode and
error condition) by setting the control register accordingly. Table 8–6 lists
the contents of the control register after such an event occurs for all
possible error or trigger conditions.
The remote system upgrade status register is updated by the dedicated
error monitoring circuitry after an error condition but before the factory
configuration is loaded.
Table 8–6. Control Register Contents After an Error or Reconfiguration
Trigger Condition
Reconfiguration
Error/Trigger
nCONFIG reset
nSTATUS error
CORE triggered
reconfiguration
CRC error
Wd time out
Control Register Setting
Remote Update
Local Update
All bits are 0
All bits are 0
Update register
All bits are 0
All bits are 0
PGM[6..0] = 7'b0000001
AnF = 1
All other bits are 0
All bits are 0
PGM[6..0] = 7'b0000001
AnF = 1
All other bits are 0
All bits are 0
All bits are 0
Altera Corporation
January 2008
8–19
Stratix II Device Handbook, Volume 2