EP2S180F1020C4 Datasheet, PDF (386/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Clock Modes
Figure 2–15. Stratix II and Stratix II GX Input/Output Clock Mode in Single-Port Mode Note (1)
6 LAB Row
Clocks
6
data[ ]
address[ ]
byteena[ ]
DQ
ENA
DQ
ENA
DQ
ENA
Memory Block
256 ´ 16
Data In _{512 ´ 8}
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
Address
Data Out
Byte Enable
DQ
ENA
To MultiTrack
Interconnect (2)
addressstall
Address
Clock Enable
wren
outclocken
inclocken
inclock
outclock
DQ
ENA
Write
Pulse
Generator
Write Enable
Notes to Figure 2–15:
(1) Violating the setup or hold time on the memory block address registers could corrupt the memory contents. This
applies to both read and write operations.
(2) Refer to the Stratix II Device Family Data Sheet (volume 1) of the Stratix II Device Handbook or the Stratix II GX Device
Family Data Sheet (volume 1) of the Stratix II GX Device Handbook for more information on the MultiTrack
interconnect.
Read/Write Clock Mode
Stratix II and Stratix II GX TriMatrix memory blocks can implement
read/write clock mode for simple dual-port memory. This mode uses up
to two clocks. The write clock controls the blocks’ data inputs, write
address, and write enable signals. The read clock controls the data output,
read address, and read enable signals. The memory blocks support
independent clock enables for each clock for the read- and write-side
registers. Asynchronous clear signals for the registers, however, are not
supported. Figure 2–16 shows a memory block in read/write clock mode.
2–26
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008