EP2S180F1020C4 Datasheet, PDF (415/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

External Memory Interfaces in Stratix II and Stratix II GX Devices
×32/×36 mode, eight adjacent DQS/DQ groups are combined and one
pair of DQS/DQSn pins can drive all the DQ and parity pins in the
combined groups.
Table 3–7 shows which DQS and DQSn pins are available in each mode
and package in the Stratix II or Stratix II GX device family.
Table 3–7. Available DQS and DQSn Pins in Each Mode and Package Note (1)
Mode
×4
×8/×9
×16/×18
×32/×36
Package
484-Pin FineLine BGA
484-Pin Hybrid FineLine BGA
672-Pin FineLine BGA
780-Pin FineLine BGA
7, 9, 11, 13
Odd-numbered pins only
7,11
3, 7, 11, 15
N/A
5, 13
N/A
N/A
1,020-Pin FineLine BGA
1,508-Pin FineLine BGA
All DQS and DQSn pins
Even-numbered pins only
3, 7, 11, 15
5, 13
Note to Table 3–7:
(1) The numbers correspond to the DQS and DQSn pin numbering in the Stratix II or Stratix II GX pin table. There are
two sets of DQS/DQ groups, one corresponding with the top side of the device and one with the bottom side of
the device.
1 On the top and bottom side of the device, the DQ and DQS pins
must be configured as bidirectional DDR pins to enable the DQS
phase-shift circuitry. The DQSn pins can be configured as input,
output, or bidirectional pins. You can use the altdq and
altdqs megafunctions to configure the DQ and DQS/DQSn
paths, respectively. However, Altera highly recommends that
you use the respective Altera memory controller IP Tool Bench
for your external memory interface data paths. The data path is
clear-text and free to use. You are responsible for your own
timing analysis if you use your own data path. If you only want
to use the DQ and/or DQS pins as inputs, you need to set the
output enable of the DQ and/or DQS pins to ground.
Stratix II or Stratix II GX side I/O banks (I/O banks 1, 2, 5, and 6) support
all the memory interfaces supported in the top and bottom I/O banks. For
optimal performance, use the Altera memory controller IP Tool Bench to
pick the data and strobe pins for these interfaces. Since these I/O banks
do not have any dedicated circuitry for memory interfacing, they can
support DDR SDRAM at speeds up to 150 MHz and other DDR memories
at speeds up to 200 MHz. You need to use the SSTL-18 Class I I/O
standard when interfacing with DDR2 SDRAM devices using pins in I/O
bank 1, 2, 5, or 6. These I/O banks do not support the SSTL-18 Class II and
Altera Corporation
January 2008
3–19
Stratix II Device Handbook, Volume 2