EP2S180F1020C4 Datasheet, PDF (269/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Figure 1–2. Stratix II GX PLL Locations
FPLL7CLK 7
PLLs in Stratix II and Stratix II GX Devices
CLK[15..12]
11 5
1
CLK[3..0]
2
PLLs
FPLL8CLK 8
12 6
CLK[7..4]
Enhanced PLLs
Stratix II and Stratix II GX devices contain up to four enhanced PLLs with
advanced clock management features. The main goal of a PLL is to
synchronize the phase and frequency of an internal and external clock to
an input reference clock. There are a number of components that
comprise a PLL to achieve this phase alignment.
Enhanced PLL Hardware Overview
Stratix II and Stratix II GX PLLs align the rising edge of the reference
input clock to a feedback clock using the phase-frequency detector (PFD).
The falling edges are determined by the duty-cycle specifications. The
PFD produces an up or down signal that determines whether the VCO
needs to operate at a higher or lower frequency.
Altera Corporation
July 2009
1–5
Stratix II Device Handbook, Volume 2