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EP2S180F1020C4 Datasheet, PDF (413/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1 | |||
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External Memory Interfaces in Stratix II and Stratix II GX Devices
Table 3â5. Stratix II GX DQS and DQ Bus Mode Support Note (1)
Device
Package
EP2SGX30C 780-pin FineLine BGA
EP2SGX30D
EP2SGX60C 780-pin FineLine BGA
EP2SGX60D
EP2SGX60E 1,152-pin FineLine BGA
EP2SGX90E 1,152-pin FineLine BGA
EP2SGX90F 1,508-pin FineLine BGA
EP2SGX130G 1,508-pin FineLine BGA
Number of
Ã4 Groups
18
18
36
36
36
36
Number of
Number of
Number of
Ã8/Ã9 Groups Ã16/Ã18 Groups Ã32/Ã36 Groups
8
4
0
8
4
0
18
8
4
18
8
4
18
8
4
18
8
4
Note to Table 3â5:
(1) Check the pin table for each DQS/DQ group in the different modes.
Table 3â6. Stratix II GX Non-DQS and DQ Bus Mode Support Note (1)
Device
EP2SGX30
EP2SGX60
EP2SGX90
EP2SGX130
Package
780-pin FineLine BGA
780-pin FineLine BGA
1,152-pin FineLine BGA
1,152-pin FineLine BGA
1,508-pin FineLine BGA
1,508-pin FineLine BGA
Number of
Ã4 Groups
18
18
25
25
25
25
Number of
Number of
Number of
Ã8/Ã9 Groups Ã16/Ã18 Groups Ã32/Ã36 Groups
8
4
2
8
4
2
13
6
3
13
6
3
12
6
3
12
6
3
Note to Table 3â6:
(1) Check the pin table for each DQS/DQ group in the different modes.
1 To support the RLDRAM II QVLD pin, some of the unused Ã4
DQS pins, whose DQ pins were combined to make the bigger
Ã8/Ã9, Ã16/Ã18, or Ã32/Ã36 groups, are listed as DQVLD pins
in the Stratix II or Stratix II GX pin table. DQVLD pins are for
input-only operations. The signal coming into this pin can be
captured by the shifted DQS signal like any of the DQ pins.
Altera Corporation
January 2008
3â17
Stratix II Device Handbook, Volume 2
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