EP2S180F1020C4 Datasheet, PDF (653/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Configuring Stratix II and Stratix II GX Devices
Table 7–22. Dedicated Configuration Pins on the Stratix II and Stratix II GX Device (Part 8 of 10)
Pin Name
DATA[7..1]
User Mode
Configuration
Scheme
I/O
Parallel
configuration
schemes
(FPP and
PPA)
Pin Type
Inputs
Description
Data inputs. Byte-wide configuration data is
presented to the target device on
DATA[7..0].
The V_{I H} and V_{I L} levels for this pin are
dependent on the input buffer selected by the
VCCSEL pin. Refer to the section “VCCSEL
Pin” on page 7–10 for more information.
In serial configuration schemes, they function
as user I/O pins during configuration, which
means they are tri-stated.
DATA7
After PPA or FPP configuration,
DATA[7..1] are available as user I/O pins
and the state of these pin depends on the
Dual-Purpose Pin settings.
I/O
PPA
Bidirectional In the PPA configuration scheme, the DATA7
pin presents the RDYnBSY signal after the
nRS signal has been strobed low.
The V_{I H} and V_{I L} levels for this pin are
dependent on the input buffer selected by the
VCCSEL pin. Refer to the section “VCCSEL
Pin” on page 7–10 for more information.
In serial configuration schemes, it functions as
a user I/O pin during configuration, which
means it is tri-stated.
nWS
After PPA configuration, DATA7 is available as
a user I/O and the state of this pin depends on
the Dual-Purpose Pin settings.
I/O
PPA
Input
Write strobe input. A low-to-high transition
causes the device to latch a byte of data on the
DATA[7..0] pins.
In non-PPA schemes, it functions as a user I/O
pin during configuration, which means it is
tri-stated.
After PPA configuration, nWS is available as a
user I/O pins and the state of this pin depends
on the Dual-Purpose Pin settings.
Altera Corporation
January 2008
7–101
Stratix II Device Handbook, Volume 2