EP2S180F1020C4 Datasheet, PDF (406/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

External Memory Standards
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For details on RLDRAM II, see AN 325: Interfacing RLDRAM II with
Stratix II & Stratix GX Devices.
QDRII SRAM
QDRII SRAM is the second generation of QDR SRAM devices. Both
devices can transfer four words per clock cycle, fulfilling the
requirements facing next-generation communications system designers.
QDRII SRAM devices provide concurrent reads and writes, zero latency,
and increased data throughput, allowing simultaneous access to the same
address location. QDRII SRAM is available in burst-of-2 and burst-of-4
devices. Burst-of-2 devices support two-word data transfer on all read
and write transactions, and burst-of-4 devices support four-word data
transfer
Interface Pins
QDRII SRAM uses two separate, unidirectional data ports for read and
write operations, enabling QDR data transfer. QDRII SRAM uses shared
address lines for reads and writes. QDRII SRAM burst-of-two devices
sample the read address on the rising edge of the clock and sample the
write address on the falling edge of the clock while QDRII SRAM
burst-of-four devices sample both read and write addresses on the clock’s
rising edge. Connect the memory device’s Q ports (read data) to the
Stratix II or Stratix II GX DQ pins. You can use any of the Stratix II or
Stratix II GX device user I/O pins in I/O banks 3, 4, 7, or 8 for the D ports
(write data), commands, and addresses. The control signals are sampled
on the rising edge of the clock. You can also use I/O pins in banks 1, 2, 5,
or 6 to interface with QDRII SRAM devices. However, these banks do not
have dedicated circuitry and can only support QDRII SRAM devices at
speeds up to 200 MHz. QDRII SRAM interfaces using these banks are
supported using the 1.8-V HSTL Class I I/O support.
QDRII SRAM uses the following clock signals:
■ Input clocks K and K#
■ Output clocks C and C#
■ Echo clocks CQ and CQ#
Clocks C#, K#, and CQ# are logical complements of clocks C, K, and CQ,
respectively. Clocks C, C#, K, and K# are inputs to the QDRII SRAM while
clocks CQ and CQ# are outputs from the QDRII SRAM. Stratix II and
Stratix II GX devices use single-clock mode for single-device QDRII
SRAM interfacing where the K and K# are used for write operations, and
CQ and CQ# are used for read operations. You should use both C or C#
and K or K# clocks when interfacing with a bank of multiple QDRII
SRAM devices with a single controller.
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Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008