EP2S180F1020C4 Datasheet, PDF (334/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Clocking
Tables 1–20 and 1–21 show which PLLs are available in each Stratix II and
Stratix II GX device, respectively, and which input clock pin drives which
PLLs.
Table 1–20. Stratix II Device PLLs and PLL Clock Pin Drivers (Part 1 of 2)
All Devices
EP2S60 to EP2S180 Devices
Input Pin
Fast PLLs
Enhanced
PLLs
Fast PLLs
Enhanced
PLLs
CLK0
CLK1 (2)
CLK2
CLK3 (2)
CLK4
CLK5
CLK6
CLK7
CLK8
CLK9 (2)
CLK10
CLK11 (2)
CLK12
CLK13
CLK14
CLK15
PLL5_FB
PLL6_FB
PLL11_FB
PLL12_FB
PLL_ENA
FPLL7CLK (2)
FPLL8CLK (2)
FPLL9CLK (2)
1 2 3 4 5 6 7 8 9 10 11 12
vv
v (1) v (1)
vv
v (1) v (1)
vv
v (1) v (1)
vv
v (1) v (1)
v
v
v
v
v
v
v
v
vv
v (1) v (1)
vv
v (1) v (1)
vv
v (1) v (1)
vv
v (1) v (1)
v
v
v
v
v
v
v
v
v
v
v
v
v v vvv v v v v v v v
v
v
v
1–70
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009