EP2S180F1020C4 Datasheet, PDF (742/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Transmission Line Layout
Figure 11–5 plots microstrip trace impedance with changing trace
thickness using the values in the microstrip impedance equation, keeping
trace width and dielectric height constant. Figure 11–5 shows that as trace
thickness increases, trace impedance decreases.
Figure 11–5. Microstrip Trace Impedance with Changing Trace Thickness
60
50
40
Z0 (Ω) 30
20
10
0
0.7
1.4
2.8
4.2
T (mil)
Z0
H = 5.0 mils
W = 8.0 mils
Stripline Impedance
A circuit trace routed on the inside layer of the PCB with two low-voltage
reference planes (power and/or GND) constitutes a stripline layout. You
can use the following stripline impedance equation to calculate the
impedance of a stripline trace layout:
( ) ^{Zo = 60 ln}
4H
Ω
ε_r
0.67 (T + 0.8W )
Using typical values of W = 9 mil, H = 24 mil, T = 1.4 mil, dielectric
constant and (FR-4) = 4.1 with the stripline impedance equation and
solving for stripline impedance (Z_o) yields:
Z_o=
( ) ^{60 ln}
4.1
4 (24)
Ω
0.67 (1.4) + 0.8(9)
Z_o ~ 50 Ω
Figure 11–6 shows impedance with changing trace width using the
stripline impedance equation, keeping height and thickness constant for
stripline trace.
11–6
Stratix II Device Handbook, Volume 2
Altera Corporation
May 2007