EP2S180F1020C4 Datasheet, PDF (759/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

High-Speed Board Layout Guidelines
Figure 11–29 shows series-RC parallel fly-by termination.
Figure 11–29. Series-RC Parallel Fly-By Termination
Receiver/
Load
S
Zo = 50 Ω
Pad
RT = Zo
C
Series Termination
In a series termination scheme, the resistor matches the impedance at the
signal source instead of matching the impedance at each load (see
Figure 11–30). Stratix II devices have programmable output impedance.
You can choose output impedance to match the line impedance without
adding an external series resistor. The sum of R_T and the impedance of the
output driver should be equal to Z₀. Because Altera device output
impedance is low, you should add a series resistor to match the signal
source to the line impedance. The advantage of series termination is that
it consumes little power. However, the disadvantage is that the rise time
degrades because of the increased RC time constant. Therefore, for
high-speed designs, you should perform the pre-layout signal integrity
simulation with Altera I/O buffer information specification (IBIS) models
before using the series termination scheme.
Figure 11–30. Series Termination
RT
S
Z0 = 50 Ω
L
Altera Corporation
May 2007
Differential Pair Termination
Differential signal I/O standards require an R_T between the signals at the
receiving device (see Figure 11–31). For the low-voltage differential signal
(LVDS) and low-voltage positive emitter-coupled logic (LVPECL)
standard, the R_T should match the differential load impedance of the bus
(typically 100 ).
11–23
Stratix II Device Handbook, Volume 2